JOB DESCRIPTION · To implement Logic Verification activities (verification of VHDL-based FPGA code with a simulation tool within the framework of DO-254 activities. · To prepare the documentation required throughout logic verification process
GENERAL QUALIFICATIONS · To be graduated from the "Electric-Electronics Engineering or Electronics-Communication Engineering" departments of universities. Preferably to have a Master's degree · Having at least 2 years of work experience as a Digital Design or Verification Engineer · FPGA Code (VHDL, Verilog) Design or Verification experience · Having a good command of English
ADDITIONAL QUALIFICATIONS · Using QuestaSim or similar FPGA verification, simulation tool · Developing with System Verilog language (or if the candidate is willing to work on logic verification, OOP languages, especially C++, C# or Python experience may be an advantage) · Experience with DOORS, JIRA, Gitlab and SVN tools · Using Vivado-Libero tool · Knowledge/experience about DO-254 Standards · Experience with AMC20-152A Guide
شرکت فناوری اطلاعات همراه رسپینا رادین از سال 89 شروع به کار کرده است و دارای رتبه 4 شورای عالی انفورماتیک کشور در عرصه تولید نرم افزارهای سفارش مشتری می باشد. زمینه ی اصلی فعالیت شرکت تولید نرم افزارهای سازمانی تحت وب می باشد.